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volatile uint32_t num;
num = RCC->CFGR; // 0x001D040A
// MCO=0: Microcontroller clock output, No clock
// OTGFSPRE=0: USB OTG FS prescaler, PLL VCO (2 x PLLCLK) clock is divided by 3 (PLL must be configured to output 72 MHz)
// PLLMUL=0111: PLL multiplication factor: PLL input clock x 9
// PLLXTPRE=0, LSB of division factor PREDIV1
// PLLSRC=1: Clock from PREDIV1 selected as PLL input clock
// ADCPRE=00: ADC prescaler = PCLK2 divided by 2
// PPRE2=000: APB high-speed prescaler (APB2), HCLK not divided
// PPRE1=100: APB Low-speed prescaler (APB1), HCLK divided by 2
// HPRE=0000: AHB prescaler, SYSCLK not divided
// SWS=10: System clock switch status, PLL used as system clock
// SW=10: System clock Switch, PLL selected as system clock
num = RCC->CFGR2; // 0x00010644
// I2S3SRC=0: I2S3 clock source, System clock (SYSCLK) selected as I2S3 clock entry
// I2S2SRC=0: I2S2 clock source, System clock (SYSCLK) selected as I2S2 clock entry
// PREDIV1SRC=1: PREDIV1 entry clock source, PLL2 selected as PREDIV1 clock entry
// PLL3MUL=0000: PLL3 Multiplication Factor, Reserved
// PLL2MUL=0110: PLL2 Multiplication Factor, PLL2 clock entry x 8
// PREDIV2=0100: PREDIV2 division factor, PREDIV2 input clock divided by 5
// PREDIV1=0100: PREDIV1 division factor, PREDIV1 input clock divided by 5
num = RCC->CR; // 0x0F035783
// PLL3RDY=0: PLL3 clock ready flag, PLL3 unlocked
// PLL3ON=0: PLL3 enable, PLL3 OFF
// PLL2RDY=1: PLL2 clock ready flag, PLL2 locked
// PLL2ON=1: PLL2 enable, PLL2 ON
// PLLRDY=1: PLL clock ready flag, PLL locked
// PLLON=1: PLL enable, PLL ON
// CSSON=0: Clock security system enable, Clock detector OFF
// HSEBYP=0: External high-speed clock bypass, external 3-25 MHz oscillator not bypassed
// HSERDY=1: External high-speed clock ready flag, HSE oscillator ready
// HSEON=1: HSE clock enable, HSE oscillator ON
// HSICAL=01010111: Internal high-speed clock calibration
// HSITRIM=10000: Internal high-speed clock trimming
// HSIRDY=1: Internal high-speed clock ready flag, Internal 8 MHz RC oscillator ready
// HSION=1: Internal high-speed clock enable, Internal 8 MHz RC oscillator ON
// PLL2 and PLL3 are clocked by HSE through a specific configurable divider.
// PLL2=25MHz/5*8=40MHz
// SYSCLK=PLL=40MHz/5*9=72MHz
// USB: 2*72/3=48MHz
// AHB: 72MHz
// APB1: 36MHz
// APB2: 72MHz
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